In many fields of application, it is desirable to produce an integrated circuit (IC) containing analog and digital circuits and additionally a storage medium. One example are integrated sensors, where highly precise analog circuits with sophisticated digital signal processing circuits are used on the same IC and/or are integrated in the same IC. Furthermore, it is preferred that the above integrated sensors store their calibration data in a memory. Here, no additional (extra) process step should become necessary for the memory when producing the corresponding integrated sensor.
Thus, the corresponding task to integrate a memory into an integrated circuit with analog and digital circuit parts without requiring an additional process step during production for producing the memory strongly conflicts with the requirements for the production of usual highly integrated memory circuits (memory ICs), wherein processes specifically adapted for a realization of memory structures (dedicated processes) may be used.
An EEPROM is particularly suitable for use in an integrated sensor, because here a change and/or iteration of the calibration is easily possible by multiple programming. In most cases, only a small amount of data of about 50 to 500 bits is required for the calibration of a sensor. Therefore, the EEPROMs used in connection with integrated sensors differ significantly from “dedicated” highly integrated EEPROMs in their architecture. When using an EEPROM in connection with an integrated sensor, it is particularly important to consume as little chip area as possible for the EEPROM, to be able to access the data in the EEPROM quickly, and to guarantee continued extremely high reliability. Furthermore, it has been shown that it is necessary for achieving a minimum chip area for the EEPROM to keep the requirements of drive circuits, such as high voltage switches, multiplexers and address decoders, particularly small as compared to highly integrated EEPROMs.
DE 102 14 898 A1 shows a space-saving drive circuit for programming an EEPROM using slightly adapted standard low voltage CMOS transistors. The above document shows an EEPROM architecture in which a gate control terminal of each cell is driven by a high voltage PMOS transistor and a high voltage NMOS transistor. A drain terminal of the EEPROM-NMOS transistor having a floating gate for the storage of information is connected to a standard CMOS logic via a high voltage PMOS transistor. The above patent application further shows an architecture in which a high voltage NMOS transistor is located between the drain of the EEPROM transistor and the standard CMOS logic.
U.S. Pat. No. 4,596,938 shows a series connection of channel paths of field effect transistors with electrically changeable threshold voltage between operational voltage clamps. Here, one of the transistors is programmed to assume a conductive state, while the other one of the two transistors is programmed to assume a non-conductive state. The programming is done in response to a programming voltage applied to the two gate terminals of the transistors connected to each other. The described circuit, forms a programmable data memory (also referred to as latch). A pair of such data memories (latches) forms a programmable complementary data memory (latch). The programmable complementary data memory may be used to selectively activate a transfer gate with a complementary pair or to selectively activate a logic inverter with a complementary pair. The programmable complementary data memory may further be used to alternatively activate a transfer gate and a logic inverter. The above mode of operation may, for example, be used to selectively invert a logic input or not.
The US patent application 2004/0042272 A1 shows a semiconductor storage means with memory cells, source lines, drain lines and drive gate lines. The memory cells are arranged in a matrix. Adjacent memory cells in the column direction have one of a source line and a drain line in common. The source terminals of memory cells of two adjacent columns are connected to a common source line. The drain terminals of memory cells of two adjacent columns are further connected to a common drain line. The drain terminals of two memory cells of two columns connected to the source line are connected to different drain lines, respectively. The gate terminals of adjacent memory cells in the row direction are connected to a common drive gate line.
The international patent application WO 02/071403 A1 shows an EEPROM with reduced circuit load of a high voltage write impulse. The reduced load is achieved by dividing a field of bit cells into two or more switchable segments with common source line. Only segments with common source line containing the bit cells to be written to are connected. The other segments with common source line remain open (non-connected) and do not contribute significantly to a loading of the write impulse. The presence of several switchable segments reduces the size of the parasitic capacitance connected in the EEPROM during a write operation. Thus, the load of the write circuits is reduced.
Furthermore, an EEPROM architecture is known according to which all cells in a chain are arranged linearly. For example, FIG. 5 shows a block circuit diagram of an EEPROM architecture realized, for example, in the products KP115 and TL4997D of the applicant.
The EEPROM architecture of FIG. 5 is designated 500 in its entirety. The EEPROM architecture 500 includes a first block 510 serving as address decoder and error correction means (FEC). The first block 510 receives data to be written into the EEPROM in parallel form as parallel data signals 512 and also provides data read from the EEPROM as parallel data signals 514. The first block 510 further receives a signal 516 for activating the error correction (fee_en_i). Furthermore, the first block 510 outputs the state of the error correction via a signal 518 (fec_status_o). The EEPROM architecture 500 further comprises a plurality of, for example, 15 EEPROM banks 530 with which various addresses (for example in the range between 0 and 14) are associated. Input/output registers (I/O registers) 550 of the EEPROM banks 530 are connected to column data lines 540 running in parallel, so that several EEPROM banks 530 share the same column lines. Besides, the input/output registers 550 of the EEPROM banks 530 are respectively coupled to the actual EEPROM memory cells, here briefly referred to as EEPROM. The input/output registers 550 of the EEPROM banks 530 are further designed to receive data to be written as a serial input signal 560 and to pass them on synchronously to a clock signal 562 in the manner of a shift register. The EEPROM banks 530 are connected such that data are shifted on serially from the input/output register 550 of a first memory bank to the input/output register 550 of a following EEPROM bank. At the last EEPROM bank 530, with which, for example, the address 14 is associated, there is further available a serial output signal 570. The EEPROM structure 500 thus allows both parallel input and output of write or read data and serial input or output of the write or read data.
In other words, a basically linear sequence of EEPROM and an associated input/output register 550 is folded into several rows in the EEPROM architecture 500. In a vertical direction, an input/output line 540 is passed through for each cell per row, which is also referred to as parallel column data line 540 (bitpar_io<15:0>). For example, when reading out the data from the EEPROM bank 530 (also referred to as EEPROM row) with the address 1, the data of the EEPROM bank 530 with the address 1 are applied to the vertical parallel column data lines (bitpar_io<15:0>) by activating the corresponding EEPROM bank (EEPROM row) alone via address coding and/or address decoding. Thus, the linear structure is converted to a matrix-like structure.
The input signal 516 for activating the error correction (also referred to as fec_en_i) activates an automatic error detection and/or error correction and may thus be considered as enable signal for forward error coding (forward error coding ENable). During the automatic error detection and/or error correction, toggling of a bit in the memory may be detected and corrected due to a matrix parity code.
FIG. 6 shows an architecture of a known EEPROM cell including its associated register cell. The architecture of FIG. 6 is designated 600 in its entirety. The center of the known architecture 600 is an EEPROM memory transistor 610 with a floating gate electrode 612. The EEPROM memory transistor 610 further comprises a gate terminal 614 connected to a gate drive circuit 620. The gate drive circuit 620 includes a first high voltage PMOS transistor 622 operating as current source. The gate drive circuit 620 further includes a first, high voltage NMOS transistor 624, whose drain terminal is coupled to the drain terminal of the first high voltage PMOS transistor 622 and to the gate terminal 614 of the EE PROM-NMOS transistor 610. A source terminal of the first high voltage NMOS transistor 624 is further coupled to a low potential 626. A drive circuit 630 consisting of a low voltage PMOS transistor and a low voltage NMOS transistor is designed to drive the gate of the first high voltage NMOS transistor 624 so that the first high voltage NMOS transistor 624 is switched on in read operation, and to further ensure that the first high voltage NMOS transistor 624 is switched on or switched off (i.e. put into a conductive or non-conductive state) in write operation (also referred to as “write or erase operation”) depending on data 634 to be written.
A drain terminal of the EEPROM-NMOS transistor 610 may further be coupled to an input of a multiplexer and/or switch 642 via a second high voltage NMOS transistor 640. Furthermore, the EEPROM-NMOS transistor 610 may be coupled to a second (low voltage) PMOS transistor 644, which may act as current source, via the second high voltage NMOS transistor 640 to thus impress a current on the EEPROM-NMOS transistor 610.
The architecture 600 further includes an EEPROM input/output register cell 650 designed to receive or provide data to be written or read data in parallel or serial form. The architecture 600 further includes switches and/or logic to be able to pass on serial data to further EEPROM cells. In addition, the architecture 600 includes an XOR gate 660 designed to allow calculation of a parity and to receive a data value present at the output of the EEPROM input/output register cell 650 and to combine it with parity information from another EEPROM cell.
It is further to be noted that there is a supply voltage for a CMOS logic present at the source terminal of the PMOS transistor 644, which is also referred to as VDDD. Thus, the supply voltage VDD may, for example, also supply the EEPROM input/output register cell 650 and/or the XOR gate 660 and/or the multiplexer 642 with electric energy.
The following describes the procedure when programming the EEPROM memory cell 600. First, it is to be noted that the data to be written are present as logic levels in inverted form on the line 634, also referred to as bit_n. In other words, if a logical “0” is to be written, a positive voltage is present on the line 634, preferably close to VDDD, whereas when writing a logical “1”, a voltage of 0 volts is present on the line 634. When writing, a programming impulse of, for example, 20 volts is further applied to the programming voltage line 670 for a duration of, for example, about ten milliseconds (wherein the programming voltage line 670 is also referred to as write_pin).
If a logical “0” is to be programmed, the erase line 672 (also referred to as erase_pin) coupled to the source terminal of the EEPROM transistor 610 is further also at the same potential as the write voltage line 670 (write_pin). Furthermore, there is typically a voltage of 0 volts on the source line 626 for the first high voltage NMOS transistor 624, when programming. At a gate terminal of the first high voltage PMOS transistor 622, there is further typically a potential about 1 to 2 volts lower than the potential on the write voltage line 670, wherein the write voltage line 670 is coupled to a source terminal of the first high voltage PMOS transistor 622. The first high voltage PMOS transistor 622 thus operates as a current source supplying a current approximately between 0.5 microampere and 5 microampere.
A bit to be programmed is loaded into the EEPROM input/output register cell 650 prior to actual programming. The control line 674 for the drive circuit 630, also referred to as “WorE”, is put to the supply potential VDDD of the CMOS circuit part when programming a logical “1” and when programming a logical “0”. It is to be noted that programming a logical “1” is considered to be writing, which is also designated “W” or “WRITE”. In contrast, programming a logical “0” is considered to be erasing, which is also designated “E” or “ERASE”.
If a logical “1” is to be programmed, the logical “1” is first loaded into a register cell of the EEPROM input/output register cell 650. Thus, the data line 634 with the data to be written is at 0 volt (bit_n= 0 volt), because the data to be written are present in inverted form on the data line 634. Thus, the gate terminal of the first high voltage NMOS transistor 624 becomes 0 volt and/or logically “low” via the drive circuit 630, and the first high voltage NMOS transistor 624 blocks. However, the first high voltage PMOS transistor 622 loads the gate terminal 614 of the EEPROM-NMOS transistor 610 and/or the associated circuit node up to the programming voltage. In other words, there is thus a voltage at the gate terminal 614 of the EEPROM-NMOS transistor 610 that differs only insignificantly and/or minimally from the programming voltage on the write voltage line 670. The gate terminal 614 of the EEPROM-NMOS transistor 610, which thus serves as control gate terminal, thus is at approximately 20 volts, whereas a potential of about 0 volts is supplied at the source terminal of the EEPROM-NMOS transistor 610 via the erase line 672 in the write mode (when writing a logical “1”). Thus, there is a high voltage at a gate oxide (GOX) of the EEPROM-NMOS transistor 610, so that electrons tunnel from the source terminal of the EEPROM-NMOS transistor 610 through the gate oxide to the floating gate 612 of the EEPROM-NMOS transistor 610. If subsequently the programming voltage of the write voltage line 670 is turned off, the above-mentioned electrons are caught on the floating gate electrode 612 of the EEPROM-NMOS transistor 610. Thus, a differential voltage of, for example, 3 volts is stored on a launching capacitor between the gate terminal 614 (CG1) of the EEPROM-NMOS transistor 610 and the floating gate electrode 612 (FGl) of the EEPROM-NMOS transistor. In other: words, the potential at the floating gate electrode 612 is always about 3 volts less than the potential at the gate terminal 614.
When reading out a bit from the memory cell 600, approximately an NMOS threshold voltage is applied to the erase line 672 (erase_pin). As the control line 674 (WorE) is further at 0 volts during readout, the gate terminal of the first high voltage NMOS transistor 624 is at the supply voltage VDDD of the CMOS circuit part. Thus, the first high voltage NMOS transistor 624 is conductive. Thus, for all memory cells, the gate terminal 614 of the EEPROM-NMOS transistor 610 is at the potential of a threshold voltage. In other words, the EEPROM-NMOS transistor 610 is driven so that, between its gate terminal 614 and its source terminal, a voltage drops that is approximately equal to its idle threshold voltage that results when no charge is present on the floating gate electrode. If a logical “1” was stored into the EEPROM-NMOS transistor 610, the floating gate electrode 612, as derived above, is at a lower potential than the gate terminal 614. Thus, the EEPROM-NMOS transistor 610 blocks when a voltage is present between the gate terminal 614 and its source terminal that is approximately equal to the idle threshold voltage without charge on the launching capacitor. When reading out, there is further a high logical level (short: sel_eeprom= high) on a selection line 678 (also referred to as sel_eeprom), so that the second high voltage NMOS transistor 640, whose gate terminal is coupled to the selection line 678, is conductive. A potential below the supply voltage VDDD for the CMOS circuit part by about a threshold voltage of the second PMOS transistor 644 is further supplied to the second PMOS transistor 644 via a drive line 680. In other words, the potential at the gate terminal of the second PMOS transistor 644 has approximately the value VDDD−|Vth, p|, wherein Vth,p indicates the threshold voltage of the second PMOS transistor 644. Thus, the supply voltage VDDD reduced by the PMOS threshold voltage is present at the second PMOS transistor 644. Thus, the second PMOS transistor 644 acts like a current, source impressing a small current of about 0.5 microampere to 5 microampere into a circuit node 684 also referred to as bit1. Besides, the circuit node 684 is coupled to the drain terminal of the EEPROM-NMOS transistor 610 via the conductive second high voltage NMOS transistor 640. However, since the EEPROM-NMOS transistor 610 blocks in the above case, the current supplied by the second PMOS transistor 644 charges the circuit node 684 to about the supply potential VDDD of the CMOS circuit part. The circuit node 684 thus represents a high logic level, which is also referred to and/or interpreted as logical “1” or as “HIGH level”. The switch and/or multiplexer 642 connected to an input of the EEPROM input/output register cell 650 is then switched to a position referred to as sel_eeprom_i. Thus, the circuit node 684 is switched to the input 690 of the EEPROM input/output register cell 650. There is further generated an impulse on a clock line 692, which is also referred to as clk_i, which takes and/or latches the logical state at the input 690 into a register of the EEPROM input/output register cell 650.
If the respective memory cell 600 is addressed, a switch 694, also referred to as EnableParOut_i is closed, thus putting an output 696 of the EEPROM input/output register cell 650 onto a column data line 698, also referred to as bitpar_io (cf. FIG. 5: bitpar_io<15:0>)).
The column data line 698 extends vertically, that is column-wise, across all EEPROM rows and passes the read-out bit to the output of the EEPROM, where it is available for a digital part of an integrated circuit including the described EEPROM.
The following describes the programming of a logical “0” into the shown memory cell 600. When programming a logical “0”, the output 696 (bit_ser_o) is at a low logic level (bit_ser_o=0). Thus, the data line 634 is at a potential that is approximately equal to the supply potential VDDD of the CMOS circuit part. In other words, bit_n= VDDD. Thus, the gate terminal of the first high voltage NMOS transistor 624 is changed to a potential (VDDD−Vth,n) that is below the supply voltage VDDD of the CMOS circuit part by about a threshold voltage Vth,n of an NMOS transistor. Thus, the first high voltage NMOS transistor 624 is conductive, whereby a low potential of about 0 volts is present at the gate terminal 614 of the EEPROM-NMOS transistor 610. In other words, CG1= 0 volts. At the same time, when writing a logical “0”, the erase line 672 is pulled to a high voltage of, for example, about 20 volts (erase_pin −20 volts). Thus, the full programming voltage with the inverse sign falls to the EEPROM-NMOS transistor 610 (also shortly referred to as “cell”) as compared to the programming of a logical “1”. Thus, electrons are sucked from the floating gate electrode 612. Thus, a differential voltage is created between the gate terminal 614 of the EEPROM-NMOS transistor 610 and the associated floating gate electrode 612, whose sign is opposite to that for programming a logical “1”. In this case, the floating gate electrode 612 is thus always more positive than the gate terminal 614, for example by about 3 volts.
During readout of the EEPROM cell 600, performed as described above, the EEPROM-NMOS transistor 610 is thus conductive. Thus, the circuit node 684 is pulled to a low potential (bit= 0 volts). Thus, a low logic level, also referred to as logical “0” or “low level”, is taken and/or latched into the register of the EEPROM input/output register cell 650.
The bits of several or all memory cells 600 of an EEPROM may further be XOR-ed column-wise, for example, to thus be able to execute a matrix parity check. This task may be done by the shown XOR gate 660.
In the EEPROM cell 600, which is able to store one bit and which is thus also referred to as bit cell, the parts with the highest chip area consumption are the three high voltage MOS transistors 622, 624, 640, the EEPROM-NMOS transistor 610 including launching capacitor as well as the EEPROM input/output register cell 650 including additional standard CMOS gates. Furthermore, all shown means have to be repeated for each further cell in the shown architecture 600 of the EEPROM bit cell. When a plurality of EEPROM bit cells 600 is present, this results in very high area requirements.